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The Cortex-A73, a CPU that won’t overheat — Gary explains
ARM,ARM Cortex A73,CPU,Gary Explains
Full details:
ARM has announced a new CPU core design, the Cortex-A73. It is faster, but more importantly it has great power efficiency during periods of sustained usage.
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#CortexA73 #CPU #wont #overheat #Gary #explains
Great video.
How the hell did you get this job? Samsung Exynos is build on 14nm, not 16nm. Apple A9 is build on both 14 and 16nm. Apple SoC also don’t overheat or throttle because the heat envelop is designed for the SoC at full speed. Race to idle is also why Apple stick with 2 broad cores instead of multiple high clock narrow cores.
Gary’s videos are an auto like
2:09 brrrring down
Will the note 6 have it cuz rumour has it that note 6 will have 6gb ram.
and how are they going to implement this? it will be already throttled?
I watched the video to see that, but in only had a video version of the press release.
Nobody gives a shit stop autoplaying these shitty adevertisements!
now we need only dual core a73 for budget phones
i thought A72 and SD820 will be the peak for couple of years , but ARM proved me wrong, CPU that wont over heat im so suspicious i wouldnt beleive untill i really see it , this video explained why not overheating is good , but i really want to know how is it possiple !
Who else hit the transcription button accidentally and saw that it is completely different from what Gary says, probably because of his accent?
Couldn’t make it past a couple minutes of this garbage.
Usually this guy in the video gives accurate information. But this is pure bullshit.
Good Videos Gary keep them coming ..
damn I don’t know how I missed this video. once again Gary thanks for a great video . for a 64 year old geezer I look forward to seeing your videos!! you present it in layman’s language, with a concise and natural flow in your presentation of the video. once again thanks for the great video.
damn I don’t know how I missed this video. once again Gary thanks for a great video . for a 64 year old geezer I look forward to seeing your videos!! you present it in layman’s language, with a concise and natural flow in your presentation of the video. once again thanks for the great video.
Its guys like Gary Sims who put the “authority” in Android Authority by publishing these lucid videos coupled with articles
Im going to get one of the Huawei Tablets that use the kirin 950 2.3 GHz (4 x A72)
1.8 GHz (4 x A53). Blows the doors of an Apple Airpad.
Kirin 960 16 nm FinFET Plus ARMv8‑A Cortex-A73
Cortex-A53
big.LITTLE. Not sure if Huawei have released a device based on this yet.. but i might well buy it.
I wonder when is the end of silicon? Will 10 nm be the last process shrink?
So its like my pentium 3 using a big cpu heatsink 15 years ago and intel M processor not needing heatsink now a day.
Do a video on Snapdragon 835. Does the Kryo in their is A72 or A73?
With the new 10nm architecture is possible to get big.LITTE clusters such as 4 x Cortex-A72 and 4 x Cortex-A73. I think one of those SoC with that configuration will be the Snapdragon 835 (stock cores with more L2 cache in order to represent the Kryo architecture).
jesus christ, an ARM A7(x) series CPU with 10nm and 2.8ghz, and it can hold that! that is remarkable!
Gary Explains is amazing!
Then why custom cores are developing..?
Talk about the mail g71mp8 GPU
Amazing!!! This will be wonderful for increased sustained performance!
So a Digital PID controller changing the CPU frequency, neat.
As the nm process decreases, they can reduce the voltage; thats why the overall power goes down.
Nice work Gary!!. Or should I say professor Gary.. ur explanations are so detailed.. and people really need to know the kind of chipsets powering their mobile devices before purchasing any smartphone in the stores
you didnt explain the tech behind allowing the chip to produce constant amount of heat output.
This is interesting, but I was thinking. What if like you said in another video about custom cores vs ARM cores.
If the instruction sets; Insets, are kept at different “lvls” or layers that way the chip, handling their insets, won’t heat up as much. Not as fast. They’ll compute the instruction sets faster, thus producing less heat.
Also another way could be to coat, a thing layer to cool off key target areas of said ‘RISC’ chips.
See my thinking is, there are what usually 4, so quad, cores in the common risc. Or 8. Octa.
So my thinking is. Get each other core to handle the sets. Once those turn off. Get the other two opposite cores to do the work. Then reapeat. On n off, on n off. Its be much more efficient that way. Also way faster. It’d boost speed really. As for temp it should, should, cool it down. Temp is always the tricky part.
An example of what I mean is here:
Core 00 handles the first ser of segments of the split instructions set.
Then Core 01: Stays off (cooling).
Core 02?: Handles the second half of the segmented instructions set that will later be recombined with its other half, that Core 00 is handling.
Then the next inset, comes along, Core 01 and Core 03 handles these sets. Then they are put together and so on.
Instructing, and also designing the SoC that’ll be integrated into the silicon this way will be the most important part. If its not designed correctly. It won’t work, correctly.
Watching this in 2019 with phones that have heat sinks and fan addons 🙂
Probably most pro gamer on PC or mobile know CPUs can run more efficiently and more power can be generated if CPU frequencies be fixed at a level of frequency , for example most cpu working in different workloads there is top and bottom frequency but a cpu can be more powerful at a normal frequency 2.7 ghz cpu is more stable than 5ghz cpu with same architecture I know these are so basic but I mean is most important thing is how to manage the frequencies interactive is bad ondamannd is bad too schedule is good for stability actually in interactive app lunch time is more slower than ondamannd there always must be delays to open an app ( at interactive) .
Why are you playing the annoying music . Why arm has license as its just a basic instruction set copycat from others. We will design our own CPUs fully integrated with onboard OS in fpga.